Fpga pdf file

If the developed control algorithm is to be implemented on a prototyping platform, it is desirable to have a simulation tool that can represent exactly the hardware used.

It would be even more useful if the simulation software could automatically generate the necessary code from the model of the algorithm. This would avoid the daunting task of rewriting the control algorithm in another language like C for implementation. If the prototyping platform uses a Field Programmable Gate Array FPGA to run the algorithm, a newly created simulation tool can be used not only to simulate exactly the hardware but also to automatically generate the VHDL code needed for the implementation.

It provides the user with a library of blocks representing functions which can be implemented in an FPGA. It can also convert the created model into VHDL code. The use of the SG has two main advantages over traditional methods. First, the implemented algorithm is guaranteed to function exactly as in the simulation and second, there is no need to create two different models one for the simulation and one for the implementation.

E-mail address: hoang. Ricci, H. In an FPGA, multiple operations required by a control system can be executed in parallel so the algorithm can run much faster. Also, their high flexibility permits easy modification of the system functionality.

It permits accurate and fast simulation of both the power inverter and the motor. It is easy to connect the blocks of the SG and the PSB to simulate the whole system including the power circuit and the controller.

This paper presents a novel approach for the design, simulation and implementation of control al- gorithms for variable-speed drive systems using an FPGA. Next, the design procedure using the proposed method is presented to illustrate the important steps. Power System Blockset description Simulink is basically a dynamic systems simulator and cannot directly simulate electrical circuits.

To overcome this limitation a specialized toolbox is used, the PSB [2]. It consists of libraries of electric blocks and analysis tools that are used to convert electric diagrams into Simulink state—space diagrams.

The electric blocks are electrical models such as electrical sources, linear and nonlinear electric ele- ments, power electronic switches, electrical machines, electric connectors, and measurement devices sensors. When the simulation is started, Simulink use the PSB to transform the electrical circuit in a state—space representation with the steady state and initial conditions of state variables. After the initial conversion, normal simulation begins. State—space formulation allows the use of a wide variety of fixed step and variable step algorithms available in Simulink.

For small- and medium-size systems, variable time step algorithms are usually faster because the number of steps is less than with a fixed time step method. Simulation results can be displayed on Simulink scopes or sent to workspace or disk file while the simulation is running. The user can access a variety of MATLAB functions and toolboxes for processing and plotting of waveforms from stored data.

Its purpose is to provide an easy-to-use high-level programming tool for FPGA users. First, the generated VHDL code is transformed into a standard schematic circuit by a synthesizer program. Then, the schematic is transformed by an implementation tool into a configuration file that can be downloaded to the FPGA.

Furthermore, the implemented code is guaranteed to perform exactly as in the simulation because the SG blocks represent exactly the FPGA hardware. This reduces the implementation time because the algorithm needs to be modeled and simulated only once. First, all the mathematical operations are done in fixed-point format. For each function, a precision must be given in the MN format where M is the number of bits representing the integer and N is the number of bits representing the fraction.

Floating point arithmetic in FPGA is possible but too much logic is required. Control algorithms can be readily implemented in fixed-point format by using appropriate scaling.

Another difference is that SG blocks work only in fixed time step. FPGA usually uses registered logic that requires a clock which means that the simulation time step represents one clock cycle in the FPGA. It can be noted that the frequency in the FPGA does not depend on the time step chosen for the simulation.

The SG library contain many blocks that are classified in five sections: 1. Basic elements: Contains simple signal processing functions delay, down sample, multiplexers, reg- isters,. Math: Contains common mathematical functions add, multiplication, relational, negate,. Many of these blocks are replicas of standard Simulink blocks. So it is easy to build a model the same way than with standard Simulink blocks. Some complex functions like division and inverse trigonometric functions are missing.

Some System Generator blocks. These two blocks represent the boundaries of the SG model. Everything inside them can be implemented. The conversion is automatic. The only thing needed to be specified is the FPGA model that will be used. The generated code can be then used to incorporate the control algorithm in an FPGA. Modeling and simulation of a complete drive system The creation of a Simulink model for the power section and the control algorithm needs a few steps that can be separated in two main parts.

The detailed steps are illustrated in the flow diagram in Fig. The first step is to determine the parameters of the power electronic section and use them to cre- ate a model using the PSB blocks. Also the hardware section of the prototyping board like the ADC can be simulated with a mathematical model. In this way, the control algorithm will be simulated as an exact replica of the real system.

The next step is the building of the control algorithm with the use of SG blocks only [5]. Yes Fig. Variable-speed drive controller design and implementation process. Interconnection between the control system and the power circuit. The fourth step is the simulation of the complete system in Simulink.

Variable or fixed time step can be used for the PSB section but the SG blocks will always simulate in discrete time. Due to the nature of the SG blocks, the simulation time tend to be higher than with standard blocks.

Because each SG block represents an exact replica of an implemented function, many operations are necessary even for a simple addition. Only the model of the targeted FPGA needs to be chosen, everything else is automatic. Usually, the FPGA will contain other functions in addition to the algorithm, communication for example. The algorithm must therefore be connected to the remainder of the VHDL code. This code is created only once and comes with the prototyping platform. A standard interface or a VHDL edition software can be used to join all the code parts.

The last step is the synthesis and implementation of the VHDL code. The term instantiation is used to refer to when a module or other resource is added to your design.

It means that an instance of that module or other resource is created. When you write code, each time you call a function the exact same instructions are used over and over again no matter how many times the function is called. However, every time you instantiate a module, the entire circuit that composes the module is duplicated. If you want to reuse the same resources for multiple tasks, it is your job as the designer to figure out how you are going to juggle that.

Speaking of instantiation, typically you instantiate everything your module needs right after the port declaration. You should think of them as wires. A wire can have a value, but it is really just a connection from one point to another. Instantiating this module is what the next couple of lines do. To instantiate anything, you simply use the name of the resource followed by the name of this particular instance. The block that this instantiation is wrapped in is called a connection block.

This block allows you to connect an input or parameter with a given name of many modules to the same signal. In our case, we are connecting the input clk to the signal clk which is an input to our module. The syntax is. Almost every module will have a clk input and often they will have a rst input for a reset. Exactly what a clock and reset are used for will be covered later.

You can also nest the blocks and since not every block that uses clk uses rst - usually you will see something of the following form in the beginning of a module. Always blocks are where you describe all the logic that happens in your module. They contain something known as combinational logic.

Combinational logic is any digital circuit whose output is a function solely of the current inputs. They have no internal state or memory. A good example of this is an addition circuit.

The output is solely determined by the two numbers currently being input. The output is always a function of the current inputs. Inside the always block we write statements. The statements are composed of four main types.

Assignments , if statements , case statements , and for loops. Assignments are by far the most common. You have some signal on the left followed by an equals sign and then an expression. The power of these comes from the expression. Here you can use a handful of different operators to manipulate bits. This is because division is too complicated for the tools to have a reasonable default to drop in for you.

Division is still possible, it just requires a bit more effort and planning. If the expression following the if is true non-zero then the first set of lines are valid. If it is false zero the lines in the else block are valid. The else portion is optional. Notice I said valid and not executed. It can be easy to fall into the trap when you have if statements and for loops to get in the programming mindset.

If statements are most often realized in hardware with a multiplexer. You are simply selecting one of two inputs based on some expression. When you assign a signal a value in an always block, no matter what the conditions are, it must be assigned a value. This usually means that if you assign a value to something in an if statement you should have a matching assignment in the else portion of the statement.

Another way to ensure you always assign a value is to begin your always block with some reasonable default values. Take a look at the following pseudo-code:. However, what happens when the button is pressed? Does led get assigned a value of 0 then updated with a value of 1?

When the button is pressed, led always has a value of 1. Assignments lower in an always block take precedence over previous assignments. They are simply like wires connecting two things together. These work exactly the same as if statements but are just a simpler way to have many branches on a single expression.

The value part of the case statement needs to be some constant. The optional default branch is a catch all. They are solely for code clarity and convenience. Finally we get to for loops. For loops in Lucid share the syntax to C or Java for loops but have some restrictions:.

The big restriction on for loops in hardware is that they must have a constant number of iterations. This is because the tools need to be able to unroll the loop. A for loop is no different than copy pasting that section of code over and over again except it is much easier to read. You should typically avoid them unless you have a good reason to use one.

It is very easy to create a very large and slow circuit using for loops. In Lucid, there are a handful of ways to define a numeric constant. The easiest way is to simply type the number like When you see a lone number, it is in decimal radix of 10 and the number of bits used to represent it are the minimum required in an unsigned format, unless it is negative.

If you want more control over the number of bits used, you can prefix the number with xd where x is the number of bits to be used. For example, 8d14 is the decimal value 14 represented with 8 bits.

You can trade out the d for h to use hexadecimal radix of 16 , or b for binary radix of 2. With both of these formats you can specify the number of bits to use before the letter. If you omit the number of bits, hexadecimal numbers default to using 4 bits per digit. For example, h08 uses 8 bits since I wrote two digits even though the value 8 could be represented with only 4 bits.

For binary, the number of bits is simply the number of digits when not explicitly specified. So, b is six bits wide. If a decimal number is written with the d but the number of bits omitted, it behaves the same as if the d was omitted as well. Many signals you will encounter will be multi-bit signals like the led input in our top-level module.

Bits in an array can be individually indexed using the syntax signal[bit] where bit is some expression. It is your job to ensure that the value will always fall within the bounds of the array if it is a dynamic value.

You can also access subsets of the bits using the array syntax [max:min]. Here the range of bits starting at min and going to max , inclusive, are selected. When using this syntax, both values need to be constants. Here start is the lowest bit to be selected and width is the number of bits to select above it including the start bit.

With this syntax, only width needs to be constant. You can also use the slight variation [start-:width]. With this syntax, start is the highest bit in the selection instead of the lowest. Arrays in Lucid can be multi-dimensional. When declaring them you simply tack on some extra dimensions like this:. You can then index the array using the selectors as before.

Note that you can only use the sub-array selections as the last selector though. Here is where things get really interesting. Combinational logic is very important but a system without any state or memory is pretty limited. So how do you create memory? Essentially you just need some kind of feedback loop. If you want to create a counter, you simply add one to the result of the last addition.

The problem is, how do you control this loop? At first glance this may seem like a non-issue, but upon deeper inspection the Pandora's Box of issues become obvious. We could create it using an adder with one of the input values fixed at 1. If we connect its input to the output we create an incrementing counter right? Well, let me raise some questions. What value does this counter start at and how fast does it count? The initial value would depend on how the power in the circuit was applied and how the circuit was laid out.

It would also likely depend on the temperature and other environmental factors. This is because an addition circuit, like most combinational logic with multi-bit outputs, produces wrong intermediate results. In the case of an adder, the least-significant bit is calculated first with each following bit using the result of the previous bit in its calculations. Since there is nothing waiting for the result to be valid, the wrong intermediate values are fed back into the adder which propagates more wrong values until the thing is just generating garbage.

So how do we fix this? We simply need a way to control the timing of the feedback loop. This is where DFFs, or D-type flip flops, are useful. Before we dive into what exactly a DFF is, let me explain what a clock is. A clock is simply a signal that toggles from 0 to 1 over and over again at some set frequency. The clock on the Alchitry boards toggles at MHz, or million times a second.

This regular signal can be used to give out circuits a sense of time. The transition from 0 to 1 is known as the rising edge and is typically the important part of the signal. These edges are marked with arrows in the above image.

DFFs are a type of memory. They have an input, D, and an output, Q. When their clock input changes from 0 to 1, the value of D is saved and output on Q until the next rising edge of the clock.

In the above diagram, the DFF is shown with the optional enable and reset signals. The enable can be used to stop the DFF from copying in a new value on a rising edge. The reset signal is used to force the Q value to a known value. Now we can use the reset signal to set the initial value to something, for example 0. That means we know Q is 0. If Q is 0, then D will be 1.

On the rising edge of the clock, Q will get the value of D. That means Q becomes 1 and that means D becomes 2. There are of course some restrictions on that. The clock needs to be slow enough so that the value at D has time to update after Q changes. This is the amount of time from a change of the inputs to the output being valid and stable.

The more logic you add, the longer this delay. The delay is also a function of the technology used to fabricate the circuit. The tools have models for each FPGA and if you tell it the clock frequency you are using, they will attempt to layout your design so that the timing requirements will be met.